1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically to a semiconductor memory device having a delay circuit for controlling a timing of an internal control signal.
2. Description of the Background Art
In a semiconductor memory device called a DRAM (Dynamic Random Access Memory), an internal control signal is generated by a control circuit in response to an external control signal such as a row address strobe signal /RAS or column address strobe signal /CAS. The internal control signal controls an operation of each circuit in the DRAM and, for example, activates a signal, which determines a timing at which a word line is activated, or a sense amplifier. The word line, sense amplifier or the like is activated in response to the rise or fall of the internal control signal. A timing at which the internal control signal rises or falls is controlled by a delay amount from a delay circuit provided in the control circuit. The delay circuit includes a buffer and a capacitor.
When a power supply voltage supplied for the delay circuit provided in the control circuit changes, a driving current for the buffer also changes accordingly, whereby the delay amount from the delay circuit changes. Thus, the power supply voltage supplied for the delay circuit in the control circuit is desirably kept at a constant level. In a conventional DRAM shown in FIG. 6, however, a power supply voltage VDD supplied for an output buffer 100 and that supplied for a delay circuit DL0 in a control circuit CTL0 are both supplied from a power supply pin P0. In addition, the change in the power supply voltage due to an operation of output buffer 100 is generally large. Accordingly, the power supply voltage supplied for delay circuit DL0 in control circuit CTL0 considerably changes by the operation of output buffer 100. As a result, the delay amount from delay circuit DL0 in control circuit CTL0 changes, thereby seriously hindering an accurate timing control for a reading/writing operation of a data signal.